Direct digital synthesis (DDS) is a digital signal processing technique that creates (i.e. “synthesizes”) sinusoids and other types of waveforms from a single precision fixed-frequency reference clock. FIG. 1 is a drawing showing the principal elements of a typical DDS 100. The DDS 100 comprises a phase accumulator 102; a phase-to-amplitude (φ-to-p) converter 104; a digital-to-analog converter (DAC) 106; and a low-pass filter (LPF) 108. The phase accumulator 102 is a synchronous sequential device which on each cycle of a reference clock (denoted by “fREF” in FIG. 1) produces an n-bit digital number representing the instantaneous phase φ of the final DDS output waveform being synthesized. On each cycle of the reference clock, the output of the accumulator 102 is fed back to an n-bit adder 110 and summed with an n-bit “tuning word” M. This results in the accumulator 102 incrementing (i.e., “accumulating”) by a “step” equal to the value of the tuning word M, on each cycle of the reference clock. The accumulator 102 keeps accumulating in this manner until the n-bit digital number it is accumulating exceeds the capacity (2n−1) of its n-bit output register 112, in other words, until the output register 112 “overflows.” When this overflow condition occurs, the overflow bit is discarded, leaving only the remainder (i.e., the “residual”) in the output register 112, and the accumulator 102 repeats the accumulation process once again.
To further visualize the operation of the accumulator 102, it can be helpful to use a diagram known as a “phase wheel” (see FIG. 2). Assuming, for example, that the accumulator 102 of the DDS 100 depicted in FIG. 1 has a word width of n=4, a tuning word of M=0011, and an initial phase accumulator output of 0000, the phasor in the phase wheel representing the accumulator 102 output rotates counterclockwise around the wheel, step-by-step, (by a “step size” of M=0011), and on each tick of the reference clock, until the accumulated result exceeds 1111 and the accumulator's output register overflows. Each traversal of the phase wheel represents one cycle 1/fOUT of the accumulator's final output OUT. The rate at which the phasor rotates about the phase wheel is determined by reference clock frequency fREF, and the number of steps (samples) made in each cycle of fOUT is determined by the value of the tuning word M relative to 2n. For a given reference clock frequency fREF, the output frequency fOUT can be increased by increasing the value of M, but at the expense of a reduced number of samples per cycle 1/fOUT.
The phase wheel in FIG. 2 further reveals how each step of the rotating phasor represents the instantaneous phase φ of the waveform being synthesized. For example, the first n-bit digital number value 0011 produced by the accumulator 102 after the accumulator has been initialized to 0000 represents an instantaneous phase of φ=3π/8 radians (67.5 degrees), the second accumulated n-bit digital number of value 0110 represents an instantaneous phase of φ=3π/4 radians (135 degrees), and so on.
The phase-to-amplitude (φ-to-p) converter 104, which is typically implemented as a sine look-up table (LUT) in a read-only memory (ROM), converts the sequence of n-bit digital numbers produced by the accumulator 102 into a digital waveform (most often a sinusoid, but other waveforms are also possible). (Note that in circumstances where the accumulator size (i.e., “accumulator width” n) is large, the n-bit digital samples produced by accumulator 102 are usually truncated so that only the p most significant bits (MSBs) are used to address the LUT. In this way, the LUT is maintained at a manageable size.) The sequence of n-bit digital samples produced at the output of the φ-to-p converter 104 is therefore a digital sinusoid of frequency fOUT=(M/2n)×fREF. The DAC 106 converts the digital sinusoid into a quantized analog waveform (e.g., a quantized analog voltage), and the LPF 108 operates to remove aliasing images and quantization noise, to produce the final, desired and smooth sinusoidal output OUT.
The DDS 100 has a number of important advantages over more conventional phase-locked loop based (PLL-based) waveform generators. Some of these advantages include: a much wider tuning bandwidth; superior frequency agility, and micro-hertz frequency-tuning and sub-degree phase-tuning capabilities. These attributes make the DDS 100 a desirable candidate for use in radar and radio frequency (RF) communications applications. One limitation of the DDS 100, however, is that there is a limit on how high the output frequency fOUT can be made. For a given word width n, the output frequency fOUT can be increased by increasing the value of the tuning word M and/or by increasing the reference clock frequency fREF. However, these two parameters cannot be increased without limit. The Nyquist-Shannon sampling theorem dictates that M<2n-1, and the maximum possible reference clock frequency that can be applied to the DDS 100 is limited by the processing delay of its accumulator 102. These limitations on the DDS's 100's maximum possible output frequency fOUT therefore pose a problem, particularly if it is desired to employ the DDS 100 in radar or microwave communication applications operating at very high frequencies, for example, 10 GHz and higher.